EEPROM (Electrically Erasable Programmable Read Only Memory) enables electrical erasing and writing of data and may be capable of retaining data even when there is no power. Electrical erasing and programming may be performed using tunneling, so that a user is able to change the information stored in the EEPROM. However, EEPROMs are often configured such that each cell includes two transistors, which may create complexities in applications (e.g. relatively larger area consumption and relatively high price) compared to an EPROM.
Non-volatile memory may be advantageous because stored data is not lost even when the power is off. Non-volatile memory may be used in the field of data storage, such as PC BIOS, set top boxes, printers, network servers, digital cameras, mobile phones, and similar devices.
With reference to the appended drawings, a related art single poly EEPROM device will be described below.
FIG. 1A illustrates a program operation by way of channel hot electron injection, in accordance with the related art. A specific voltage may be induced to a floating gate by program voltage +Vp being applied to an N-well (e.g. the voltage induced to the floating gate is determined by a coupling ratio). A channel region of NMOS (N-Metal Oxide Semiconductor) may be inversed by the specific voltage induced to, the floating gate.
When a specific voltage VDS is applied to a drain region of NMOS, current flows toward a source from the drain and channel hot electrons generated in the vicinity of a drain junction region are injected into the floating gate, thereby increasing a threshold voltage of the NMOS device.
FIG. 1B illustrates an erase operation by way of a F/N (Fowler-Nordheim) tunneling, in accordance with the related art. An N-well may be grounded and an erase voltage +VE may be applied to the source/drain of NMOS. A potential that is approximately at ground may be induced to the floating gate by the ground voltage being applied to the N-well. An electric field may be strongly biased toward the floating gate from the source/drain of NMOS by the erase voltage +VE applied to the source/drain of NMOS. The electrons that are present in the floating gate may escape into the source/drain regions via F/N tunneling under the applied electric field, thereby decreasing the threshold voltage of the NMOS device.
FIG. 1C illustrates a read operation in an EEPROM, in accordance with the related art. A read voltage +VR may be applied to an N-well, whereby a specific voltage may be induced to a floating gate. A positive drain voltage for reading may be applied to the drain of an NMOS device and the source of the NMOS device may be grounded.
If the threshold voltage of the NMOS device is very high under a programming condition where electrons are injected into the floating gate, the NMOS device cannot be turned on even with the specific voltage induced to the floating gate. Since the NMOS device cannot be turned on, no current flows. In an erase condition wherein electrons are absent in the floating gate, the threshold voltage of the NMOS device may be very low and therefore the NMOS device can be turned on even with the specific voltage induced to the floating gate, so that current may flow.
In some related art EEPROM devices, a tunnel oxide layer may be formed between the floating gate and the N-well and channel hot electrons that are generated in the vicinity of the drain junction region may be trapped using the tunnel oxide layer. However, using the tunnel oxide layer may be problematic because a voltage higher than the voltage biased from the source to the drain should be applied to the floating gate, which may undesirably affect other devices. For this reason, when voltage is not sufficiently applied to the floating gate there may be undesirable decreases in reliability of a device.
In some related art single poly EEPROM cells, because the N-well should be formed to enable a specific potential to be induced to the floating gate so as to execute program/erase/read operations, the unit cell area is relatively large, making it difficult to implement. EEPROMs at a high density.